Download e-book for kindle: A Pipelined Multi-core MIPS Machine: Hardware Implementation by Mikhail Kovalev, Silvia M. Müller, Wolfgang J. Paul

By Mikhail Kovalev, Silvia M. Müller, Wolfgang J. Paul

ISBN-10: 3319139053

ISBN-13: 9783319139050

ISBN-10: 3319139061

ISBN-13: 9783319139067

This monograph relies at the 3rd author's lectures on desktop structure, given in the summertime semester 2013 at Saarland college, Germany. It incorporates a gate point building of a multi-core computer with pipelined MIPS processor cores and a sequentially constant shared memory.

The publication comprises the 1st correctness proofs for either the gate point implementation of a multi-core processor and in addition of a cache dependent sequentially constant shared reminiscence. This opens how one can the formal verification of synthesizable for multi-core processors within the future.

Constructions are in a gate point version and hence deterministic. against this the reference versions opposed to which correctness is proven are nondeterministic. the advance of the extra equipment for those proofs and the correctness evidence of the shared reminiscence on the gate point are the most technical contributions of this work.

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Additional resources for A Pipelined Multi-core MIPS Machine: Hardware Implementation and Correctness Proof

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The only way to guarantee constant register outputs during the time period is not to clock the register during that time. We require the reset signal to behave like an output of a register which is clocked at cycles −1 and 0 and is not clocked afterwards (Fig. 21): ⎧ ⎪ ⎨1 t ∈ [e(−1) + σ, e(0) + ρ] reset(t) = Ω t ∈ (e(0) + ρ, e(0) + σ) ⎪ ⎩ 0 otherwise . Special signals 1 and 0 are always said to be 1 or 0 respectively: 1(t) = 1 0(t) = 0 . 3 Clocked Circuits a in1 b in2 α y 47 hold(y, t) β a◦b reg(y, t) Fig.

Assume a path s[0 : k] with k > #G exists in the circuit. All si are gates except possibly s0 which might be an input. Thus, a gate must be (at least) twice on the path: ∃i, j : i < j ∧ si = sj . Then s[i : j] is a cycle3 . 3 This proof uses the so called pigeonhole principle. If k + 1 pigeons are sitting in k holes, then one hole must have at least two pigeons. 2 Some Basic Circuits 33 Since every path in a circuit has finite length, one can define for each signal s the depth d(s) of s as the number of gates on a longest path from an input to s: d(s) = max{m | ∃ path s[0 : m] : s0 ∈ In ∧ sm = s} .

17. 3 Clocked Circuits We introduce two computational models in which processors are constructed and their correctness is proven. We begin with the usual digital hardware model, where time is counted in hardware cycles and signals are binary-valued. Afterwards, we present a more general, detailed hardware model that is motivated by the data sheets of hardware manufacturers. There, time is real-valued and signals may assume the digital values in B as well as a third value Ω. , in the real time systems that control cars or airplanes [10, 14], and the presence and absence of glitches.

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A Pipelined Multi-core MIPS Machine: Hardware Implementation and Correctness Proof by Mikhail Kovalev, Silvia M. Müller, Wolfgang J. Paul

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